The world's leading supplier of semiconductor solutions, TSE: 6723, announced today the development of the third generation 32-bit RX CPU core, RXv3. The RXv3 CPU core will be used in the new RX microcontroller (MCU) family of Reza Electronics, which will be officially launched by the end of 2018. The new MCU is designed to meet the needs of real-time and stronger stability for motor control and industrial applications in the next generation of smart factories, smart homes and smart infrastructure.

The innovative RXv3 core dramatically improves the proven RX CPU core architecture performance, delivering up to 5.8 CoreMark?/MHz performance (measured against the EEMBC? Benchmark) and providing industry-leading performance (notes), efficiency, and responsiveness. The RXv3 core is backward compatible with the RXv2 and RXv1 CPU cores in the current 32 bit RX MCU series of Renesas electronics. Because of the same CPU core instruction set, its binary compatibility ensures that applications written on previous generations of RXv2 and RXv1 cores can continue to be used on RXv3-based MCUs. Designers working on the RXv3-based MCU can develop their own embedded systems with the help of the powerful RXE Series development ecosystem.

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Daryl Khoo, vice president of product marketing for Reissa's Internet of Things platform business, said, "RXv3 has sophisticated kernel technology for embedded applications in the industrial Internet of Things era. In this era, the increasing complexity of the system raises higher requirements for performance and effectiveness. The EEMBC CoreMark/MHz processor benchmark clearly shows that the RXv3 core is the best CPU core in the industry. Reza Electronics has once again provided our customers with superior MCU performance and performance for the next generation of embedded systems.

Main features of RXv3 CPU core

This unique RX CPU core combines optimized efficiency design with advanced manufacturing technology to achieve excellent performance. The new RXv3 CPU core mainly uses CISC (Complex Instruction Set Computer) architecture, which has more obvious advantages in code density than RISC (Reduced Instruction Set Computer) architecture. RXv3 uses instruction pipelining to provide high cycle instruction (IPC) performance comparable to RISC. The new RXv3 core is based on a mature RXv2 architecture, with enhanced instruction pipeline, multiple options for register group storage, and dual precision floating-point unit (FPU) capabilities to achieve the best computational performance, power consumption and code efficiency.

Excellent computing performance and efficiency

Enhanced RX core five-stage superscalar architecture allows instruction pipelines to execute more instructions at the same time, while maintaining excellent power efficiency.

The RXv3 core will enable the first batch of new RX600 MCUs to achieve 44.8 CoreMark/mA energy efficiency, using an energy-efficient cache design to reduce access time and power consumption for on-chip flash memory reads (such as extracting instructions).

The fastest response speed

RXv3 core saves this new feature option through a single-cycle register, significantly shortening the interrupt response time

By using dedicated instructions and a set of saved registers with up to 256 memory areas, designers can minimize the interrupt processing overhead required to run embedded systems in real-time applications such as motor control.

With the help of register group preservation function, the RTOS process context switching time can be shortened by 20%.

Unparalleled dual precision FPU function

Model-based development (MBD) has penetrated into all kinds of application development; using DP-FPU can help reduce the amount of work required to migrate high-precision control models to MCUs

Similar to the RXv2 core, the RXv3 core performs both DSP/FPU operations and memory access, greatly improving signal processing capabilities